The CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to four differential pairs of clock outputs (Y[0:3], Y[0:3]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all.
erential clock input pair (CLK, CLK) to four differential pairs of clock outputs (Y[0:3], Y[0:3]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state), and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit detects the low-frequency condition and after ap.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | CDCV850 |
Texas Instruments |
2.5-V Phase Lock Loop Clock Driver | |
2 | CDCV850I |
Texas Instruments |
2.5-V Phase Lock Loop Clock Driver | |
3 | CDCV855I |
Texas Instruments |
2.5-V PHASE-LOCK LOOP CLOCK DRIVER | |
4 | CDCV857A |
Texas Instruments |
2.5-V PHASE LOCK LOOP CLOCK DRIVER | |
5 | CDCV857B |
Texas Instruments |
2.5-V PHASE LOCK LOOP CLOCK DRIVER | |
6 | CDCV857BI |
Texas Instruments |
2.5-V PHASE LOCK LOOP CLOCK DRIVER | |
7 | CDCV304 |
Texas Instruments |
200-MHz General-Purpose Clock Buffer | |
8 | CDCV304-EP |
Texas Instruments |
General-Purpose Clock Buffer | |
9 | CDCVF111 |
Texas Instruments |
1:9 DIFFERENTIAL LVPECL CLOCK DRIVER | |
10 | CDCVF2310 |
Texas Instruments |
2.5-V to 3.3-V High-Performance Clock Buffer | |
11 | CDCVF2310-EP |
Texas Instruments |
2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER | |
12 | CDCVF2505 |
Texas Instruments |
3.3-V Clock Phase-Lock Loop Clock Driver |