CDCV850 - Texas Instruments

CDCV850 2.5-V Phase Lock Loop Clock Driver

GND 18 Y3 19 31 GND 30 Y8 The CDCV850 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock outputs Y3 20 VDDQ 21 Y4 22 Y4 23 GND 24 29 Y8 28 VDDQ 27 Y9 26 Y9 25 GND (FBOUT, FBOUT). .

Features

9 31 GND 30 Y8 The CDCV850 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock outputs Y3 20 VDDQ 21 Y4 22 Y4 23 GND 24 29 Y8 28 VDDQ 27 Y9 26 Y9 25 GND (FBOUT, FBOUT). The clock outputs are con- trolled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDATA, SCLK), and the analog power input (AVDD). A two-line serial interface can put the individual output clock pairs i.