CDC536 - Texas Instruments

CDC536 3.3-V Phase-Lock-Loop Clock Driver

The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on.

Features

• Low-Output Skew for Clock-Distribution and Clock-Generation Applications
• Operates at 3.3-V VCC
• Distributes One Clock Input to Six Outputs
• One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency
• No External RC Network Required
• External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input
• Application for Synchronous DRAM, High-Speed Microprocessor
• Negative-Edge-Triggered Clear for Half-Frequency Outputs
• TTL-Compatible Inputs and Outputs
• Outputs Drive 50-Ω Parallel-Terminated Transmission Lines
• State-of-the-Art EPIC.