CDC516 - Texas Instruments

CDC516 3.3-V Phase-Lock-Loop Clock Driver

The CDC516 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback output (FBOUT) to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC516 operates at 3.3-V VCC and is designed to drive up to five clo.

Features

. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the 1G, 2G, 3G, and 4G control inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. DGG PACKAGE (TOP VIEW) VCC 1 1Y0 2 1Y1 3 GND 4 GND 5 1Y2 6 1Y3 7 VCC 8 1G 9 GND 10 AVCC 11 CLK 12 AGND 13 AGND 14 GND 15 2G 16 VCC 17 2Y0 18 2Y1 19 GND 20 GND 21 2Y2 22 2Y3 23 VCC 24 48 VCC 47 4Y0 46 4Y1 45 GND 44 GND 43 4Y2 42 4Y3 4.