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AS4C32M16SM 512M (32M x 16) bit Synchronous DRAM (SDRAM) Confidential Preliminary (Rev. 1.0, July /2014) Revision History AS4C32M16SM Revision Details Rev 1.0 Preliminary datasheet Date July 2014 Confidential 1|P a g e Rev1.0, July 2014 AS4C32M16SM Confidential 512M (32M x 16) bit Synchronous DRAM (SDRAM) Preliminary (Rev. 1.0, July /2014) Featur.
PC133-compliant
Configurations
– 32 Meg x 16 (8 Meg x 16 x 4 banks)
Fully synchronous; all signals registered on positive edge of system clock
Internal, pipelined operation; column address can be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto precharge, includes concurrent auto precharge and auto refresh modes
Self refresh mode
Auto refresh
–64ms, 8192-cycle refresh (commercial and industrial)
LVTTL-compatible inputs and outputs
Single 3.3V ±0.3V power supply
Operating temperature range
o.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | AS4C32M16SA |
Alliance Semiconductor |
512Mbit Single-Data-Rate (SDR) SDRAM |
|
| 2 | AS4C32M16SB-6TIN |
Alliance Semiconductor |
CMOS synchronous 512Mb SDRAM |
|
| 3 | AS4C32M16SB-7TCN |
Alliance Semiconductor |
CMOS synchronous 512Mb SDRAM |
|
| 4 | AS4C32M16SB-7TIN |
Alliance Semiconductor |
CMOS synchronous 512Mb SDRAM |
|
| 5 | AS4C32M16SC-7TIN |
Alliance Semiconductor |
512M SDRAM |
|
| 6 | AS4C32M16D1 |
Alliance Semiconductor |
32M x 16 bit DDR Synchronous DRAM |
|
| 7 | AS4C32M16D1A-C |
Alliance Semiconductor |
32M x 16 bit DDR Synchronous DRAM |
|
| 8 | AS4C32M16D1A-I |
Alliance Semiconductor |
32M x 16 bit DDR Synchronous DRAM |
|
| 9 | AS4C32M16D2 |
Alliance Semiconductor |
512M (32M x 16 bit) DDRII Synchronous DRAM |
|
| 10 | AS4C32M16D2A-25BAN |
Alliance Semiconductor |
32M x 16 bit DDR2 Synchronous DRAM |
|
| 11 | AS4C32M16D2A-25BCN |
Alliance Semiconductor |
32M x 16 bit DDR2 Synchronous DRAM |
|
| 12 | AS4C32M16D2A-25BIN |
Alliance Semiconductor |
32M x 16 bit DDR2 Synchronous DRAM |
|