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74LS75 - Hitachi Semiconductor

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74LS75 Quadruple Bistable Latches

19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) + 0.13 DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 16 9 5.5 1 *0.22 ± 0.05 0.20 ± 0.04 8 0.80 Max 2.20 Max 0.20 7.80 + – 0.30 1.15 0° – 8° 0.70 ±.

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s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high q.

The same part from a different manufacturer

Datasheet 74LS75 - Motorola 74LS75

4-BIT D LATCH The TTL/MSI SN54/ 74LS75 and SN54/ 74LS77 are latches used as temporary storage for binary information bet.

Datasheet 74LS75 - Fairchild Semiconductor 74LS75

These latches are ideally suited for use as temporary storage for binary information between processing units and input/.

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