Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7.80 – 0.30 1.15 0° – 8° + 0.20 1.42 Max 1.27 *0.4.
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This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data.
SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS / 74LS73A offers individual J, K, clear, and clock inp.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74LS73A |
Fairchild Semiconductor |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops | |
2 | 74LS73A |
Hitachi Semiconductor |
Dual J-K Flip-Flops | |
3 | 74LS74 |
ON Semiconductor |
LOW-POWER SCHOTTKY | |
4 | 74LS74 |
Fairchild Semiconductor |
Dual Positive-Edge-Triggered D Flip-Flops | |
5 | 74LS74 |
Hitachi Semiconductor |
Dual D-type Positive Edge-triggered Flip-Flops | |
6 | 74LS74 |
National Semiconductor |
Dual Positive-Edge-Triggered D Flip-Flops | |
7 | 74LS74 |
Motorola |
DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP | |
8 | 74LS74 |
Texas Instruments |
Dual D-Type Positive-Edge-Triggered Flip-Flop | |
9 | 74LS74A |
Texas Instruments |
Dual D-Type Positive-Edge-Triggered Flip-Flop | |
10 | 74LS75 |
Fairchild Semiconductor |
Quad Latch | |
11 | 74LS75 |
Hitachi Semiconductor |
Quadruple Bistable Latches | |
12 | 74LS75 |
Motorola |
4-BIT D LATCH |