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74LS73 |
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| Part Number | 74LS73 |
| Manufacturer | Fairchild Semiconductor |
| Description | This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The cloc... |
| Features |
uit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs CLR L H H H H H CLK X ↓ ↓ ↓ ↓ H J X L H L H X K X L L H H X Q0 Q L Q0 H L Toggle Q0 Outputs Q H Q0 L H
H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level ↓ = Negative going edge of pulse. Q0 = The output logic level before the indicated input conditions were established. Toggle = Each output changes to the complem... |
| Document |
 74LS73 Data Sheet
PDF 53.28KB |
| Distributor | Stock | Price | Buy |
|---|
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | 74LS73 |
Hitachi Semiconductor |
Dual J-K Flip-Flops |
|
| 2 | 74LS73 |
Motorola |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
|
| 3 | 74LS73A |
Fairchild Semiconductor |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops |
|
| 4 | 74LS73A |
Hitachi Semiconductor |
Dual J-K Flip-Flops |
|
| 5 | 74LS74 |
ON Semiconductor |
LOW-POWER SCHOTTKY |
|