DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will .
individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse. SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIAGRAM (Each Flip-Flop) Q 5(9) CLEAR (CD) 15(14) J 3(11) 1(13) C.
This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74LS112 |
Hitachi Semiconductor |
Dual J-K Negative-edge-triggered Flip-Flops | |
2 | 74LS11 |
Fairchild Semiconductor |
Triple 3-Input AND Gate | |
3 | 74LS114A |
Motorola |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | |
4 | 74LS10 |
ON Semiconductor |
TRIPLE 3-INPUT NAND GATE | |
5 | 74LS10 |
Fairchild Semiconductor |
Triple 3-Input NAND Gate | |
6 | 74LS107 |
ETC |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops | |
7 | 74LS109 |
Agere Systems |
Dual J-K Flip-Flop | |
8 | 74LS109A |
ON Semiconductor |
LOW POWER SCHOTTKY | |
9 | 74LS109A |
Texas Instruments |
Dual J-K Positive-Edge-Triggered Flip-Flops | |
10 | 74LS12 |
Hitachi Semiconductor |
Dual Retriggerable Monostable Multivibrators | |
11 | 74LS12 |
Fairchild Semiconductor |
Dual Retriggerable One-Shot | |
12 | 74LS12 |
ON Semiconductor |
LOW POWER SCHOTTKY |