Recherchez avec le numéro de pièce ainsi que le fabricant ou la description
This device contains three independent gates each of which performs the logic AND function. Ordering Code: Order Number DM74LS11M DM74LS11N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in T.
te Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4..
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | 74LS10 |
ON Semiconductor |
TRIPLE 3-INPUT NAND GATE |
|
| 2 | 74LS10 |
Fairchild Semiconductor |
Triple 3-Input NAND Gate |
|
| 3 | 74LS107 |
ETC |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops |
|
| 4 | 74LS109 |
Agere Systems |
Dual J-K Flip-Flop |
|
| 5 | 74LS109A |
ON Semiconductor |
LOW POWER SCHOTTKY |
|
| 6 | 74LS109A |
Texas Instruments |
Dual J-K Positive-Edge-Triggered Flip-Flops |
|
| 7 | 74LS112 |
Hitachi Semiconductor |
Dual J-K Negative-edge-triggered Flip-Flops |
|
| 8 | 74LS112A |
Motorola |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
|
| 9 | 74LS112A |
Fairchild Semiconductor |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
|
| 10 | 74LS114A |
Motorola |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
|
| 11 | 74LS12 |
Hitachi Semiconductor |
Dual Retriggerable Monostable Multivibrators |
|
| 12 | 74LS12 |
Fairchild Semiconductor |
Dual Retriggerable One-Shot |
|