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PLL102-10 |
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| Part Number | PLL102-10 |
| Manufacturer | PhaseLink Corporation |
| Description | The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchro... |
| Features |
Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs. • Zero input - output delay. • Less than 700 ps device - device skew. • Less than 250 ps skew between outputs. www.DataSheet4U.com • Less than 100 ps cycle - cycle jitter. • 2.5V or 3.3V power supply operation. • Available in 8-Pin SOIC or MSOP package. • • PIN CONFIGURATION REFIN GND CLK1 CLK2 1 8 CLKOUT DNC DNC VDD PLL102-10 2 3 4 7 6 5 DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high s... |
| Document |
 PLL102-10 Data Sheet
PDF 213.29KB |
| Distributor | Stock | Price | Buy |
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| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | PLL102-108 |
PhaseLink Corporation |
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| 2 | PLL102-109 |
PhaseLink Corporation |
Programmable DDR Zero Delay Clock Driver |
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| 3 | PLL102-15 |
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Low Skew Output Buffer |
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| 4 | PLL102-03 |
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| 5 | PLL102-04 |
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