No. | Partie # | Fabricant | Description | Fiche Technique |
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Samsung Semiconductor |
64Kx36-Bit Synchronous Burst SRAM • Synchronous Operation. • On-Chip Address Counter. • Write Self-Timed Cycle. • On-Chip Address and Control Registers. • VDD= 3.3V+0.3V/-0.165V Power Supply. • VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. • 5V |
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Samsung Semiconductor |
(KM736V749 / KM718V849) 128Kx36 & 256Kx18 Pipelined NtRAM • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. • Byte Writable Function. • Enable clock and suspend operation. • Single READ/WRITE control pin. • Self-Timed Write Cycle. • |
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Samsung Semiconductor |
(KM736V749 / KM718V849) 128Kx36 & 256Kx18 Pipelined NtRAM • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. • Byte Writable Function. • Enable clock and suspend operation. • Single READ/WRITE control pin. • Self-Timed Write Cycle. • |
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Samsung Semiconductor |
128Kx36 Synchronous SRAM • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers. • VDD= 3.3V+0.3V/-0.165V Power Supply. • VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V |
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Samsung Semiconductor |
(KM736V747 / KM718V847) 128Kx36 & 256Kx18 Flow-Through NtRAM • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O • Byte Writable Function. • Enable clock and suspend operation. • Single READ/WRITE control pin. • Self-Timed Write Cycle. • T |
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Samsung Semiconductor |
(KM736V747 / KM718V847) 128Kx36 & 256Kx18 Flow-Through NtRAM • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O • Byte Writable Function. • Enable clock and suspend operation. • Single READ/WRITE control pin. • Self-Timed Write Cycle. • T |
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Samsung Semiconductor |
128Kx36 Synchronous SRAM • Synchronous Operation. • On-Chip Address Counter. • Write Self-Timed Cycle. • On-Chip Address and Control Registers. • VDD= 3.3V+0.3V/-0.165V Power Supply. • VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. • 5V |
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Samsung Semiconductor |
128Kx36 Synchronous SRAM • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers. • VDD= 3.3V+0.3V/-0.165V Power Supply. • I/O Supply Voltage 2.5V+0.4V/-0.13V. • 5V Tole |
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Samsung Semiconductor |
64Kx36-Bit Synchronous Burst SRAM Synchronous Operation. On-Chip Address Counter. Write Self-Timed Cycle. On-Chip Address and Control Registers. Single 3.3V ±5% Power Supply. 5V Tolerant Inputs except I/O Pins. Byte Writable Function. Global Write Enable Controls a full bus-width wri |
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Samsung semiconductor |
(KM736V887 / KM718V987) 256Kx36 & 512Kx18 Synchronous SRAM • Synchronous Operation. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers. • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O • 5V To |
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Samsung Semiconductor |
128Kx36 Synchronous SRAM • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers. • VDD= 3.3V+0.3V/-0.165V Power Supply. • VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V |
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Samsung semiconductor |
512Kx36 & 1Mx18 Synchronous SRAM • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers. • VDD= 3.3V +0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V +0.165V/-0.165V for |
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Samsung semiconductor |
512Kx36 & 1Mx18 Synchronous SRAM • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers. • VDD= 3.3V +0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V +0.165V/-0.165V for |
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Samsung Semiconductor |
64Kx36-Bit Synchronous Pipelined Burst SRAM • • • • • • • • • • • • • • • • • Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter. Self-Timed Write Cycle. On-Chip Address and Control Registers. VDD= 3.3V+0.3V/-0.165V Power Supply. VDDQ Supply Voltage 3.3V+0 |
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Samsung Semiconductor |
64Kx36-Bit Synchronous Pipelined Burst SRAM • • • • • • • • • • • • • • • • Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter. Self-Timed Write Cycle. On-Chip Address and Control Registers. VDD= 3.3V-5%/+10% Power Supple 5V Tolerant Inputs Except I/O Pins |
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Samsung semiconductor |
(KM736FV4021 / KM718FV4021) 128Kx36 & 256Kx18 Synchronous Pipelined SRAM • • • • • • • • • • • • 128Kx36 or 256Kx18 Organizations. 3.3V Core Power Supply. LVTTL Input and Output Levels. Differential, PECL Clock Inputs K, K. Synchronous Read and Write Operation Registered Input and Registered Output Internal Pipeline Latch |
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Samsung semiconductor |
(KM736FV4021 / KM718FV4021) 128Kx36 & 256Kx18 Synchronous Pipelined SRAM • • • • • • • • • • • • 128Kx36 or 256Kx18 Organizations. 3.3V Core Power Supply. LVTTL Input and Output Levels. Differential, PECL Clock Inputs K, K. Synchronous Read and Write Operation Registered Input and Registered Output Internal Pipeline Latch |
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Samsung Semiconductor |
32Kx32-Bit Synchronous Pipelined Burst SRAM • • • • • • • • • • • • • • • • • Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter. Self-Timed Write Cycle. On-Chip Address and Control Registers. VDD = 3.3V-5%/+10% Power Supply 5V Tolerant Inputs except I/O P |
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Samsung Semiconductor |
32Kx32-Bit Synchronous Pipelined Burst SRAM • • • • • • • • • • • • • • • • • Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter. Self-Timed Write Cycle. On-Chip Address and Control Registers. VDD = 3.3V-5%/+10% Power Supply 5V Tolerant Inputs except I/O P |
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Samsung Semiconductor |
32Kx32-Bit Synchronous Pipelined Burst SRAM • • • • • • • • • • • • • • • • • Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter. Self-Timed Write Cycle. On-Chip Address and Control Registers. Core Supply Voltage : 3.3V±5% 5V Tolerant Inputs except I/O Pin |
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