No. | Partie # | Fabricant | Description | Fiche Technique |
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Integrated Silicon Solution |
36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM DESCRIPTION 1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Common I/O read and write ports. Synchronous pipeline read with self-timed late write operation. Double Data Rate (DDR) inter |
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Integrated Silicon Solution |
32K x 8 LOW POWER CMOS STATIC RAM • Access time: 25 ns, 45 ns • Low active power: 200 mW (typical) • Low standby power — 150 µW (typical) CMOS standby — 15 mW (typical) operating • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 5V po |
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Integrated Silicon Solution |
4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory SEPTEMBER 2013 • Single Power Supply Operation - Low voltage range: 3.0 V - 3.6 V • Standard Intel Firmware Hub/LPC Interface - Read compatible to Intel® 82802 Firmware Hub devices - Conforms to Intel LPC Interface Specification Revision 1.1 • Memo |
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Integrated Silicon Solution |
256K x 36/ 512K x 18 9Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pi |
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Integrated Silicon Solution |
CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER • 80C51 based architecture • 8K x 8 ROM (IS80C52 only) • 256 x 8 RAM www.DataSheet4U.com • Three 16-bit Timer/Counters • Full duplex serial channel • Boolean processor • Four 8-bit I/O ports, 32 I/O lines • Memory addressing capability – 64K ROM and |
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Integrated Silicon Solution |
1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE • TTL compatible inputs and outputs; tristate I/O • Refresh Interval: — Auto refresh Mode: 1,024 cycles /16 ms — RAS-Only, CAS-before-RAS (CBR), and Hidden — Self refresh Mode - 1,024 cycles / 128ms • JEDEC standard pinout • Single power supply: — 5V |
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Integrated Silicon Solution |
256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE • TTL compatible inputs and outputs • Refresh Interval: 512 cycles/8 ms • Refresh Mode : RAS-Only, CAS-before-RAS (CBR), and Hidden • JEDEC standard pinout • Single power supply: 3.3V ± 10% • Byte Write and Byte Read operation via two CAS • Lead-free |
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Integrated Silicon Solution Inc |
64K x 32 SYNCHRONOUS PIPELINE STATIC RAM • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Three chip enables for simple depth expansion a |
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Integrated Silicon Solution Inc |
SRAM • • • • • • • • • • • • • • • • 100 percent bus utilization No wait cycles between Read and Write Internal self-timed write cycle Individual Byte Write Control Single R/W (Read/Write) control pin Clock controlled, registered address, data and control |
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Integrated Silicon Solution |
512K x 8 High Speed CMOS Static RAM |
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Integrated Silicon Solution |
CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER • 80C51 based architecture • 8K x 8 ROM (IS80C52 only) • 256 x 8 RAM www.DataSheet4U.com • Three 16-bit Timer/Counters • Full duplex serial channel • Boolean processor • Four 8-bit I/O ports, 32 I/O lines • Memory addressing capability – 64K ROM and |
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Integrated Silicon Solution |
4M x 4 bit DYNAMIC RAM WITH EDO PAGE MODE • Extended Data-Out (EDO) Page Mode access cycle • TTL compatible inputs and outputs • Refresh Interval: -- 2,048 cycles/32 ms • Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden • JEDEC standard pinout • Single power supply: 5V ± 10% or 3.3V |
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Integrated Silicon Solution |
4M x 4 bit DYNAMIC RAM WITH EDO PAGE MODE • Extended Data-Out (EDO) Page Mode access cycle • TTL compatible inputs and outputs • Refresh Interval: -- 2,048 cycles/32 ms • Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden • JEDEC standard pinout • Single power supply: 5V ± 10% or 3.3V |
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Integrated Silicon Solution |
512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM • Clock frequency: 100 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11 (bank select) • Single 1.8V power supply • LVTTL inter |
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Integrated Silicon Solution Inc |
CMOS SINGLE CHIP 8-BIT MICROCONTROLLER with 8-Kbytes of FLASH • 80C51 based architecture • 8-Kbytes of on-chip Reprogrammable Flash Memory • 256 x 8 RAM • Three 16-bit Timer/Counters • Full duplex serial channel • Boolean processor • Four 8-bit I/O ports, 32 I/O lines • Memory addressing capability – 64K ROM an |
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Integrated Silicon Solution Inc |
64K x 64 SYNCHRONOUS PIPELINE STATIC RAM • Fast access time: – 117, 100 MHz • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Five chip en |
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Integrated Silicon Solution Inc |
SRAM • • • • • • • • • • • • • • • • 100 percent bus utilization No wait cycles between Read and Write Internal self-timed write cycle Individual Byte Write Control Single R/W (Read/Write) control pin Clock controlled, registered address, data and control |
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Integrated Silicon Solution |
36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM DESCRIPTION 1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Common I/O read and write ports. Synchronous pipeline read with self-timed late write operation. Double Data Rate (DDR) inter |
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Integrated Silicon Solution |
36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM DESCRIPTION 1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Common I/O read and write ports. Synchronous pipeline read with self-timed late write operation. Double Data Rate (DDR) inter |
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Integrated Silicon Solution |
18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM DESCRIPTION 512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid window. Common I/O read and write ports. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for |
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