No. | Partie # | Fabricant | Description | Fiche Technique |
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Cypress Semiconductor |
Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs • High-speed, low-power, first-in, first-out (FIFO) memories • 64 x 9 (CY7C4421V) • 256 x 9 (CY7C4201V) • 512 x 9 (CY7C4211V) • 1K x 9 (CY7C4221V) • 2K x 9 (CY7C4231V) • 4K x 9 (CY7C4241V) • 8K x 9 (CY7C4251V) • High-speed 66-MHz operation (15-ns rea |
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Cypress Semiconductor |
32K/64Kx18 Deep Sync FIFOs • High-speed, low-power, first-in first-out (FIFO) memories • 32K x 18 (CY7C4275) • 64K x 18 (CY7C4285) • 0.5 micron CMOS for optimum speed/power • High-speed 100-MHz operation (10-ns read/write cycle times) • Low power — ICC=50 mA • • • • • • • • • |
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Cypress Semiconductor |
256K (32K x 8) Static RAM ■ Temperature range ❐ –40 °C to 85 °C ■ Pin and function compatible with CY7C199C ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 80 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 3 mA ■ 2.0 V data retention ■ Automatic power-down when deselecte |
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Cypress Semiconductor |
36-Mbit (1M x 36) Pipelined Sync SRAM ■ Supports bus operation up to 250 MHz ■ Available speed grade is 250 MHz ■ Registered inputs and outputs for pipelined operation ■ 2.5-V core power supply ■ 2.5-V I/O power supply ■ Fast clock-to-output times ❐ 2.5 ns (for 250-MHz device) ■ Provide |
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Cypress Semiconductor |
16-Mbit (1M x 16) Static RAM ■ High speed ❐ tAA = 10 ns ■ Embedded error-correcting code (ECC) for single-bit error correction ■ Low active power ❐ ICC = 90 mA typical ■ Low CMOS standby power ❐ ISB2 = 20 mA typical ■ Operating voltages of 3.3 ± 0.3 V ■ 1.0 V data retention ■ Tr |
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Cypress Semiconductor |
2K x 8 Reprogrammable PROM • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 20 ns (Commercial) — 35 ns (Military) • Low power — 660 mW (Commercial and Military) • Low standby power — 220 mW (Commercial and Military) • EPROM technology 100% program |
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Cypress Semiconductor |
18-Mbit Burst of 4 Pipelined SRAM Functional Description • Separate independent Read and Write data ports • Supports concurrent transactions • 167-MHz clock for high bandwidth • 2.5 ns Clock-to-Valid access time • 4-Word Burst for reducing the address bus frequency • Double Data Ra |
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Cypress Semiconductor |
(CY7B9910 / CY7B9920) Low Skew Clock Buffer • • • • • • • • • All outputs skew <100 ps typical (250 max.) 15- to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs Outputs drive 50Ω terminated lines Low operating current 24-pin SOIC package Jitter: <200 ps peak to peak, |
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Cypress Semiconductor |
High-Speed USB Peripheral Controller ■ USB 2.0 USB IF Hi-Speed certified (TID # 40460272) ■ Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor ■ Fit-, form-, and function-compatible with the FX2 ❐ Pin-compatible0 ❐ Object-code-compatible ❐ Functional |
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Cypress Semiconductor |
144-Mbit QDR-IV HP SRAM ■ 144-Mbit density (8M ×18, 4M ×36) ■ Total Random Transaction Rate [1] of 1334 MT/s ■ Maximum operating frequency of 667 MHz ■ Read latency of 5.0 clock cycles and write latency of 3.0 clock cycles ■ Two-word burst on all accesses ■ Dual independent |
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Cypress Semiconductor |
USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD) • 128 macrocells in eight logic array blocks (LABs) • 20 dedicated inputs, up to 64 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology • Available in 84-pin CLCC, PLCC, and 100-pin PGA, PQFP The 1 |
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Cypress Semiconductor |
72-Mbit QDR II+ SRAM Four-Word Burst Architecture ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 550 MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces on both read and write ports (data transfe |
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Cypress Semiconductor |
72-Mbit DDR-II SRAM Two-Word Burst Architecture ■ 72-Mbit density (4M × 18, 2M × 36) ■ 333 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timi |
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Cypress Semiconductor |
1.8V Synchronous Pipelined SRAM ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 2 |
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Cypress Semiconductor |
(CY7C68300B / CY7C68301B / CY7C68320 / CY7C68321) EZ-USB AT2LPTM USB 2.0 to ATA/ATAPI Bridge (CY7C68300B/CY7C68301B and CY7C68320/CY7C68321) • Support for CompactFlash and one ATA/ATAPI device • Can place the ATA interface in high-impedance (Hi-Z) to allow sharing of the ATA bus with another controller (e.g., an IEEE-1394 to ATA bridge chip |
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Cypress Semiconductor |
(CY7C4282 / CY7C4292) 64K/128K x 9 Deep Sync FIFOs • High-speed, low-power, first-in first-out (FIFO) memories • 64K × 9 (CY7C4282) • 128K × 9 (CY7C4292) • 0.5-micron CMOS for optimum speed/power • High-speed, near-zero latency (true dual-ported memory cell), 100-MHz operation (10-ns read/write cycle |
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Cypress Semiconductor |
3.3V/2.5V Programmable Skew Clock Buffer • All output pair skew <100 ps (typical) • Input Frequency Range: 3.75 MHz to 200 MHz • Output Frequency Range: 3.75 MHz to 200 MHz • User-selectable output functions — Selectable skew to 18 ns — Inverted and non-inverted — Operation at 1⁄2 and 1⁄4 i |
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Cypress Semiconductor |
Low Voltage Microcontroller ■ Powerful Harvard Architecture processor ❐ M8C processor speeds running up to 24 MHz ❐ Low power at high processing speeds ❐ Interrupt controller ❐ 1.71 V to 3.6 V operating voltage ❐ Commercial temperature range: 0 °C to +70 °C ■ Flexible on-chip m |
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Cypress Semiconductor |
Low-Voltage Microcontroller ■ enCoRe II low-voltage (enCoRe II LV) – enhanced component reduction ❐ Internal crystalless oscillator with support for optional external clock or external crystal or resonator ❐ Configurable I/O for real world interface without external components |
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Cypress Semiconductor |
3-Mbit (128K x 24) Static RAM I Highspeed Ë tAA = 10 ns I Low activepower Ë ICC = 175 mA at f= 100 MHz I Low CMOS standbypower Ë ISB2 = 25 mA I Operatingvoltages of3.3 ±0.3 V I 2.0 V data retention I Automatic power-downwhendeselected I Transistor-transistorlogic (TTL) compatible |
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