ZL30117 - Zarlink Semiconductor

ZL30117 SONET/SDH Low Jitter Line Card Synchronizer

. . . 9 1.1 DPLL Features . . . . . . . 9 1.2 DPLL Mode Of Operation . ..

Features

• Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813 Internal APLL provides standard output clock frequencies from 6.48 MHz up to 622.08 MHz with jitter less than 1 ps RMS for OC-48/STM-16 interfaces Programmable output synthesizer generates clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz Digital Phase Locked-Loop (DPLL) provides all the features necessary for generating SONET/SDH compliant clocks including automatic hitless.