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ZL30117 |
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| Part Number | ZL30117 |
| Manufacturer | Zarlink Semiconductor |
| Description | . . . . . 9 1.1 DPLL Features.. ... |
| Features |
• Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813 Internal APLL provides standard output clock frequencies from 6.48 MHz up to 622.08 MHz with jitter less than 1 ps RMS for OC-48/STM-16 interfaces Programmable output synthesizer generates clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz Digital Phase Locked-Loop (DPLL) provides all the features necessary for generating SONET/SDH compliant clocks including automatic hitless... |
| Document |
 ZL30117 Data Sheet
PDF 303.88KB |
| Distributor | Stock | Price | Buy |
|---|
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | ZL30110 |
Zarlink Semiconductor |
Telecom Rate Conversion DPLL |
|
| 2 | ZL30111 |
Zarlink Semiconductor |
POTS Line Card PLL |
|
| 3 | ZL30112 |
Zarlink Semiconductor |
SLIC/CODEC DPLL |
|
| 4 | ZL30116 |
Zarlink Semiconductor |
SONET/SDH Low Jitter System Synchronizer |
|
| 5 | ZL30119 |
Zarlink Semiconductor |
Low Jitter Line Card Synchronizer |
|