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The TC58NVG5D2 is a single 3.3 V 32 Gbit (36,393,025,536 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192 + 376) bytes × 128 pages × 4148 blocks. The device has two 8568-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 8568-byte incre.
• Organization
Memory cell array Register Page size Block size
TC58NVG4D2E 8568 × 518.5K × 8 8568 × 8 8568 bytes (1M + 47 K) bytes
• Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Mullti Page Read
• Mode control Serial input/output
Command control
• Number of valid blocks Min 3936 blocks Max 4148 blocks
• Power supply VCC = 2.7 V to 3.6 V
• Access time
Cell array to register 200 µs max
Serial Read Cycle
25 ns min
• Program/Erase time Auto Page Program
Auto Block Erase
1600 µs/page typ. 4.5 ms/bl.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | TC58NVG5D2FTA00 |
Toshiba |
32 GBIT (4G X 8 BIT) CMOS NAND E2PROM |
|
| 2 | TC58NVG5D2FTAI0 |
Toshiba |
32 GBIT (4G X 8 BIT) CMOS NAND E2PROM |
|
| 3 | TC58NVG5T2HTA00 |
Toshiba |
32 GBIT (4G X 8 BIT) CMOS NAND E2PROM |
|
| 4 | TC58NVG0S3AFT00 |
Toshiba |
1 GBit CMOS NAND EPROM |
|
| 5 | TC58NVG0S3AFT05 |
Toshiba |
1 GBit CMOS NAND EPROM |
|
| 6 | TC58NVG0S3ETA00 |
Toshiba |
1 GBIT (128M X 8 BIT) CMOS NAND E2PROM |
|
| 7 | TC58NVG0S3HBAI4 |
Toshiba |
1G BIT (128M x 8-BIT) CMOS NAND E2PROM |
|
| 8 | TC58NVG0S3HBAI6 |
Toshiba |
1G-BIT (128M x 8 BIT) CMOS NAND E2PROM |
|
| 9 | TC58NVG0S3HTA00 |
Toshiba |
1 GBIT (128M x 8 BIT) CMOS NAND E2PROM |
|
| 10 | TC58NVG0S3HTAI0 |
Toshiba |
1 GBIT (128M x 8 BIT) CMOS NAND E2PROM |
|
| 11 | TC58NVG1S3BFT00 |
Toshiba |
2-GBit CMOS NAND EPROM |
|
| 12 | TC58NVG1S3EBAI4 |
Toshiba |
2 GBIT (256M x 8-BIT) CMOS NAND E2PROM |
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