SUD50N025-25P - Vishay Siliconix

SUD50N025-25P N-Channel MOSFET

The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capac.

Features

physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 73393 S-50907Rev. A, 16-May-05 www.vishay.com 1 SPICE Device Model SUD50N025-05P Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a www.DataSheet4U.com Symbol Test Condition Simulated Data 1.8 1013 0.0041 .