STW51000 - ST Microelectronics

STW51000 SUPER INTEGRATED DSP ENGINE

GreenSIDE is a cost-effective, System-on-Chip device that targets applications in wireless infrastructure equipment. The device combines two quad-MAC ST140 DSP cores, a standard ARM926-EJS RISC processor core providing a total of 29000 Mops, 7500 Mips, 4800MMacs/s, 16Mb of embedded SRAM memory, dedicated Turbo Decoding Engine (TDE) for Data error correction.

Features

Figure 1. Package
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■ Super Integrated SoC including 2 x ST140 quad MAC DSP engines running at 600MHz and 1 x ARM926 Micro Controller running at 300MHz Double Quad-MAC units Double Quad-ALU (32 and 40-bit) PBGA/HSP-569 4800 MMacs/s - 29000 Mops - 7500 Mips Convolutional Decoder Engine: Table 1. Order Codes
  – 256 x 12.2 kpbs AMR voice users Part Number Package
  – Programmable Code Parameters to support STW51000AT PBGA/HSP-569 multi-standards (W-CDMA, TD-SCDMA, CDMA2000 and EDGE) Turbo Decoder Engine:
■ Conditional Instructions to reduce code size an.