STE110NS20FD - ST Microelectronics

STE110NS20FD N-Channel Power MOSFET

Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patented STrip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(ON) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and .

Features

(1) VISO Tstg Tj January 2002 Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuos) at TC = 25°C Drain Current (continuos) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Insulation Winthstand Voltage (AC-RMS) Storage Temperature Max. Operating Junction Temperature INTERNAL SCHEMATIC DIAGRAM Value 200 200 ±20 110 69 440 500 4 25 2500
  –65 to 150 150 (1)ISD ≤110A, di/dt ≤ 200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX Unit V V V A A A W W/°C V/ns V °C °C (
•)Pulse widt.