SN74F126 - Texas Instruments

SN74F126 QUADRUPLE BUS BUFFER GATE

ordering information The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. D, N, OR NS PACKAGE (TOP VIEW) 1OE 1 1A 2 1Y 3 2OE 4 2A 5 2Y 6 GND 7 14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y To ensure the high-impedance state during power up or power down, .

Features

independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. D, N, OR NS PACKAGE (TOP VIEW) 1OE 1 1A 2 1Y 3 2OE 4 2A 5 2Y 6 GND 7 14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP
  – N Tube SN74F126N SN74F126N 0°C to 70°C SOIC
  – D Tube.