SN74F109 - Texas Instruments

SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOP

These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K input meeting the setup-time requirements are transferred to the outputs on the positive-going ed.

Features

D-type flip-flops if J and K are tied together. The SN54F109 is characterized for operation over the full military temperature range of
  – 55°C to 125°C. The SN74F109 is characterized for operation from 0°C to 70°C. SN54F109 . . . J PACKAGE SN74F109 . . . D OR N PACKAGE (TOP VIEW) 1CLR 1 1J 2 1K 3 1CLK 4 1PRE 5 1Q 6 1Q 7 GND 8 16 VCC 15 2CLR 14 2J 13 2K 12 2CLK 11 2PRE 10 2Q 9 2Q SN54F109 . . . FK PACKAGE (TOP VIEW) 1J 1CLR NC VCC 2CLR 1K 1CLK NC 1PRE 1Q 3 2 1 20 19 4 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2J 2K NC 2CLK 2PRE 1Q GND NC 2Q 2Q NC
  – No internal connection FUNCT.