SMOMAPL138B-HIREL - Texas Instruments

SMOMAPL138B-HIREL Low-Power Applications Processor

SMOMAPL138B-HiRel www.ti.com SLVSAQ9B – JANUARY 2011 – REVISED JULY 2013 SMOMAPL138B Low-Power Applications Processor Check for Samples: SMOMAPL138B-HiRel 1 SMOMAPL138B Low-Power Applications Processor 1.1 Features 123 • Highlights – Compact 16-Bit Instructions – Dual Core SoC • C674x Two Level Cache Memory Architecture • 375-MHz ARM926EJ-S™ RISC MPU.

Features

123
• Highlights
  – Compact 16-Bit Instructions
  – Dual Core SoC
• C674x Two Level Cache Memory Architecture
• 375-MHz ARM926EJ-S™ RISC MPU
  – 32K-Byte L1P Program RAM/Cache
• 375-MHz C674x Fixed/Floating-Point VLIW
  – 32K-Byte L1D Data RAM/Cache DSP
  – 256K-Byte L2 Unified Mapped RAM/Cache
  – Enhanced Direct-Memory-Access Controller
  – Flexible RAM/Cache Partition (L1 and L2) (EDMA3)
• Enhanced Direct-Memory-Access Controller 3
  – Serial ATA (SATA) Controller (EDMA3):
  – DDR2/Mobile DDR Memory Controller
  – 2 Channel Controllers
  – Two Multimedia Card (MMC)/Secure Digital
  – 3 Transfer.