The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capaci.
physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70550 S-60142Rev. B, 13-Feb-06 www.vishay.com 1 SPICE Device Model Si6955ADQ Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Currenta Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltage a.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | Si6953DQ |
Vishay |
Dual P-Channel 20-V (D-S) MOSFET | |
2 | Si6953DQ |
Fairchild Semiconductor |
Dual 20V P-Channel PowerTrench MOSFET | |
3 | SI6954ADQ |
Vishay Siliconix |
N-Channel MOSFET | |
4 | SI6954DQ |
Vishay Siliconix |
Dual N-Channel MOSFET | |
5 | Si6956DQ |
Vishay |
Dual N-Channel 20-V (D-S) MOSFET | |
6 | SI6911DQ |
Vishay Siliconix |
Dual P-Channel MOSFET | |
7 | SI6913DQ |
Vishay Siliconix |
Dual P-Channel 12-V (D-S) MOSFET | |
8 | SI6924AEDQ |
Vishay Siliconix |
N-Channel MOSFET | |
9 | SI6924EDQ |
Vishay Siliconix |
N-Channel MOSFET | |
10 | SI6925ADQ |
Vishay Siliconix |
MOSFET | |
11 | SI6925DQ |
Vishay Siliconix |
Dual N-Channel MOSFET | |
12 | SI6926ADQ |
Vishay Siliconix |
MOSFET |