SAA7110 - NXP

SAA7110 One Chip Front-end 1 OCF1

QUICK REFERENCE DATA ORDERING INFORMATION SYSTEM VIEW BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Analog input processing (see Fig.5) Analog control circuits Chrominance processing (see Fig.6) Luminance processing (see Fig.7) YUV-bus (digital outputs) Synchronization (see Fig.7) Clock generation circuit Power-on reset RTCO output GAIN CHARTS LIMITING VALUES.

Features

APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION SYSTEM VIEW BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Analog input processing (see Fig.5) Analog control circuits Chrominance processing (see Fig.6) Luminance processing (see Fig.7) YUV-bus (digital outputs) Synchronization (see Fig.7) Clock generation circuit Power-on reset RTCO output GAIN CHARTS LIMITING VALUES CHARACTERISTICS TIMING OUTPUT FORMATS CLOCK SYSTEM Clock generation circuit Power-on control I2C-BUS DESCRIPTION I2C-bus format I2C-bus receiver/transmitter tables I2C-bus detail I2C-bus detail (continued) .