PHP3055L - NXP

PHP3055L PowerMOS transistor Logic level FET

N-channel enhancement mode logic level field-effect power transistor in a plastic envelope featuring high avalanche energy capability, stable blocking voltage, fast switching and high thermal cycling performance with low thermal resistance. Intended for use in Switched Mode Power Supplies (SMPS), motor control circuits and general purpose switching applicati.

Features

ar derating factor Gate-source voltage Non-repetitive gate-source voltage Single pulse avalanche energy Peak avalanche current Operating junction and storage temperature range CONDITIONS Tmb = 25 ˚C; VGS = 10 V Tmb = 100 ˚C; VGS = 10 V Tmb = 25 ˚C Tmb = 25 ˚C Tmb > 25 ˚C tp ≤ 50 µs VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω; VGS = 5 V VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω; VGS = 5 V MIN. - 55 MAX. 12 9 48 50 0.33 ± 15 ± 20 25 6 175 UNIT A A A W W/K V V mJ A ˚C THERMAL RESISTANCES SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to.