P30NS15LFP - STMicroelectronics

P30NS15LFP STP30NS15LFP

Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charg.

Features

n Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Single Pulse Avalanche Energy Peak Diode Recovery voltage slope Storage Temperature Operating Junction Temperature Value 150 150 ± 15 10 7 40 30 0.2 300 2.4 -55 to 175 (1) Starting T j = 25 oC, ID = 15A, VDD= 75V (2) ISD ≤35A, di/dt ≤300A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. Unit V V V A A A W W/°C mJ V/ns °C (
•) Pulse width limited by safe operating area. July 2003 . 1/9 Datasheet pdf - http://www.DataSheet4U.net/ www.DataSheet.co.kr STP30NS15LFP THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resis.