NT5DS64M8BG - Nanya Techology

NT5DS64M8BG (NT5DSxxMxBx) 512Mb DDR SDRAM

NT5DS128M4BF, NT5DS128M4BT, NT5DS64M8BF, NT5DS64M8BT, NT5DS32M16BF and NT5DS32M16BT are die B of 512Mb SDRAM devices based using DDR interface. They are all based on Nanya’s 110 nm design process. accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access. .

Features

CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 DDR266B (5T) (6K) (75B) 133 100 166 166 133 200 -
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• DDR 512M bit, die B, based on 110nm design rules
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for reads and is centeraligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for writ.