NT5DS64M8AF - Nanya Techology

NT5DS64M8AF (NT5DSxxMxAF) 512Mb DDR SDRAM

The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4, or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the bu.

Features

CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR333 DDR266B 6K 75B 133 100 166 133
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• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for reads and is centeraligned with data for writes
• Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands enter.