The 2Gb Double-Data-Rate-3 (DDR3(L)) is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs. The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 banks or 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for gener.
JEDEC DDR3 Compliant
- 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM
Signal Integrity
- Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%)
Data Integrity
- Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes
Signal Synchronization
- Write Leveling via MR settings - Read Leveling via MPR
7
Power Saving Mode
- Partial Array Self Refresh (PASR) - Power Down Mode
1
Interface and.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | NT5CB128M16BP |
Nanya |
2Gb DDR3 SDRAM B-Die | |
2 | NT5CB128M16HP |
Nanya |
2Gb DDR3 SDRAM H-Die | |
3 | NT5CB128M16IP |
Nanya |
Industrial and Automotive DDR3(L) 2Gb SDRAM | |
4 | NT5CB128M16JR |
Nanya |
Commercial and Industrial DDR3(L) 2Gb SDRAM | |
5 | NT5CB128M8AN |
Nanya |
1Gb DDR3 SDRAM A-Die | |
6 | NT5CB128M8DN |
Nanya |
1Gb DDR3 SDRAM | |
7 | NT5CB128M8FN |
Nanya |
1Gb SDRAM | |
8 | NT5CB128M8GN |
Nanya |
Industrial and Automotive DDR3(L) 1Gb SDRAM | |
9 | NT5CB1024M4BN |
Nanya |
4Gb DDR3 SDRAM B-Die | |
10 | NT5CB1024M4CN |
Nanya |
4Gb DDR3 SDRAM C-Die | |
11 | NT5CB256M16BP |
Nanya |
4Gb DDR3 SDRAM B-Die | |
12 | NT5CB256M16CP |
Nanya |
Industrial and Automotive DDR3(L) 4Gb SDRAM |