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Table 1. PIN DESCRIPTION Pin # Pin Name Type Description 1 REF_SEL Input LVCMOS/ LVTTL level input to select input reference source. Pulldown with crystal as default reference input source. 2 REF_IN Input 25 MHz single−ended reference input clock. 3 VDD 4 GND Power Ground Positive supply voltage pin connected to +3.3 V typical supply voltage. Po.
• Uses 25 MHz Fundamental Crystal or Reference Clock Input
• Four Low Skew HCSL or LVDS Outputs
• Output Frequency Selection of 100 MHz or 125 MHz
• Individual OE Tri−States Outputs
• Master Reset and BYPASS Modes
• PCIe Gen 1, Gen 2, Gen 3 Compliant
• Typical Phase Jitter @ 125 MHz (Integrated 1.875 MHz to 20 MHz):
0.2 ps
• Typical Cycle−Cycle Jitter @ 100 MHz (10k cycles): 20 ps
• Phase Noise @ 100 MHz:
Offset Noise Power 100 Hz −101 dBc/Hz 1 kHz −123 dBc/Hz 10 kHz −133 dBc/Hz 100 kHz −136 dBc/Hz 1 MHz −141 dBc/Hz 10 MHz −155 dBc/Hz
• Operating Supply Voltage Range 3.3 V ±5%
• Industrial Tem.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | NB3N51032 |
ON Semiconductor |
Dual HCSL/LVDS Clock Generator |
|
| 2 | NB3N51034 |
ON Semiconductor |
Quad HCSL - LVDS Clock Generator |
|
| 3 | NB3N51054 |
ON Semiconductor |
Quad HCSL / LVDS Clock Generator |
|
| 4 | NB3N511 |
ON Semiconductor |
3.3V / 5.0V 14MHz to 200MHz PLL Clock Multiplier |
|
| 5 | NB3N501 |
ON Semiconductor |
3.3V / 5.0V 13 MHz to 160 MHz PLL Clock Multiplier |
|
| 6 | NB3N502 |
ON Semiconductor |
14 MHz to 190 MHz PLL Clock Multiplier |
|
| 7 | NB3N508S |
ON Semiconductor |
PureEdge VCXO Clock Generator |
|
| 8 | NB3N551 |
ON Semiconductor |
Ultra-Low Skew 1:4 Clock Fanout Buffer |
|
| 9 | NB3N5573 |
ON Semiconductor |
Dual HCSL Clock Generator |
|
| 10 | NB3N106K |
ON Semiconductor |
3.3V Differential 1:6 Fanout Clock Driver |
|
| 11 | NB3N108K |
ON Semiconductor |
3.3V Differential 1:8 Fanout Clock Data Driver |
|
| 12 | NB3N111K |
ON Semiconductor |
3.3V Differential 1:10 Fanout Clock Driver |
|