MT46V4M32 - Micron Technology

MT46V4M32 DOUBLE DATA RATE DDR SDRAM

The 128Mb (x32) DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728- bits. It is internally configured as a quadbank DRAM. The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2 n prefetch architecture with an interface designed to transfer.

Features

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• VDD = +2.5V ±0.125V, VDDQ = +2.5V ±0.125V
• Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture
• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
• Reduced output drive option
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable burst lengths:.