MT41J64M16 - Micon

MT41J64M16 DDR3 SDRAM

. . . . . . .11 General Notes . . . .11 Functional Blo.

Features

DDR3 SDRAM MT41J256M4
  – 32 Meg x 4 x 8 Banks MT41J128M8
  – 16 Meg x 8 x 8 Banks MT41J64M16
  – 8 Meg x 16 x 8 Banks Features
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• VDD = VDDQ = +1.5V ±0.075V 1.5V center-terminated push/pull I/O Differential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs (CK, CK#) 8 internal banks Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11 POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2 CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on tCK Fixed burst length (BL) of 8 a.