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The M54/74HC137 is a high speed CMOS 3 TO 8LINE DECODER/LATCH (INVERTING) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device is a 3 to 8line decoder withlatches on thethree address inputs. When GL goes from low tohigh, theaddress present at theselect inputs (.
he latches. As long as GL remains high no address changes will be recognized. Output enable pins G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All the outputs are high unless G1 is high and G2 is low. The HC137 is ideally suited for the implementation of glitch-free decoders in stored-address applications in bus oriented systems. All inputs are equipped withprotection circuits against staticdischarge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection February 1993 1/11 M.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | M54HC131 |
ST Microelectronics |
3 TO 8 LINE DECODER/LATCH |
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| 2 | M54HC132 |
STMicroelectronics |
Rad-hard high speed 2V to 6V CMOS logic |
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| 3 | M54HC133 |
ST Microelectronics |
13 INPUT NAND GATE |
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| 4 | M54HC138 |
STMicroelectronics |
Rad-hard high speed 2V to 6V CMOS logic |
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| 5 | M54HC139 |
STMicroelectronics |
Rad-hard high speed 2V to 6V CMOS logic |
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| 6 | M54HC10 |
STMicroelectronics |
Rad-hard high speed 2V to 6V CMOS logic |
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| 7 | M54HC107 |
ST Microelectronics |
DUAL J-K FLIP FLOP WITH CLEAR |
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| 8 | M54HC109 |
STMicroelectronics |
Rad-hard high speed 2V to 6V CMOS logic |
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| 9 | M54HC11 |
STMicroelectronics |
Rad-hard high speed 2V to 6V CMOS logic |
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| 10 | M54HC112 |
ST Microelectronics |
DUAL J-K FLIP FLOP |
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| 11 | M54HC113 |
ST Microelectronics |
DUAL J-K FLIP FLOP |
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| 12 | M54HC123 |
STMicroelectronics |
Rad-hard high speed 2V to 6V CMOS logic |
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