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The M54/74HC131 is a high speed CMOS 3 TO 8 LINE DECODER/LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device is a DECODER/LATCH capable of selecting arbitrarily one of eight outputs by three binary inputs A, B, and C, in this case, the selected output is.
”low”. Also, when ENABLE input G1 is set low or ENABLE input G2 is set high, selection is inhibited regardless of other input signals and all the outputs are at high. All inputs are equipped with protection circuits against static discharge and transient excess voltage. October 1992 NC = No Internal Connection 1/12 M54/M74HC131 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 2, 3 4 5 6 9, 10, 11, 12, 13, 14, 15, 7 8 16 SYMBOL A, B, C CLK G2 G1 Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 GND VCC NAME AND FUNCTION Data Inputs Clock Input (LOW to HIGH, Edge-triggered) Enable (Active LOW) Ena.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | M54HC132 |
STMicroelectronics |
Rad-hard high speed 2V to 6V CMOS logic |
|
| 2 | M54HC133 |
ST Microelectronics |
13 INPUT NAND GATE |
|
| 3 | M54HC137 |
ST Microelectronics |
3 TO 8 LINE DECODER/LATCH INVERTING |
|
| 4 | M54HC138 |
STMicroelectronics |
Rad-hard high speed 2V to 6V CMOS logic |
|
| 5 | M54HC139 |
STMicroelectronics |
Rad-hard high speed 2V to 6V CMOS logic |
|
| 6 | M54HC10 |
STMicroelectronics |
Rad-hard high speed 2V to 6V CMOS logic |
|
| 7 | M54HC107 |
ST Microelectronics |
DUAL J-K FLIP FLOP WITH CLEAR |
|
| 8 | M54HC109 |
STMicroelectronics |
Rad-hard high speed 2V to 6V CMOS logic |
|
| 9 | M54HC11 |
STMicroelectronics |
Rad-hard high speed 2V to 6V CMOS logic |
|
| 10 | M54HC112 |
ST Microelectronics |
DUAL J-K FLIP FLOP |
|
| 11 | M54HC113 |
ST Microelectronics |
DUAL J-K FLIP FLOP |
|
| 12 | M54HC123 |
STMicroelectronics |
Rad-hard high speed 2V to 6V CMOS logic |
|