TECHNICAL DATA IW4029B Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS The IW4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consists of a single CLOCK, CARRY IN,(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q.
the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY IN signal is low. The CARRY IN signal in the low state can thus be considered a CLOCK ENABLE. The CARRY IN terminal must be connected to GND when not in use. PIN ASSIGNMENT Binary counting is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low. Parallel clocking provides synchronous control and hence faster response from .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | IW4020B |
IK Semiconductor |
14-Bit Binary Divide Counter | |
2 | IW4021B |
IK Semiconductor |
8-Bit Shift Register | |
3 | IW4023B |
IK Semiconductor |
Triple 3-Input NAND GAte | |
4 | IW4024B |
IK Semiconductor |
Stage Ripple-Carry Binary Counter/Divider | |
5 | IW4025B |
IK Semiconductor |
Triple 3-Input NOR Gate | |
6 | IW4027B |
IK Semiconductor |
Dual J-K Flip-Flop | |
7 | IW4028B |
IK Semiconductor |
BCD-to-Decimal Decoder | |
8 | IW4001B |
IK Semiconductor |
Quad 2-Input NOR Gate | |
9 | IW4002B |
IK Semiconductor |
Dual 4-Input NOR Gate | |
10 | IW4006B |
IK Semiconductor |
18-Bit Static Shift Register | |
11 | IW4011B |
IK Semiconductor |
Quad 2-Input NAND Gate | |
12 | IW4012B |
IK Semiconductor |
Dual 4-Input NAND Gate |