HSP9520 - Intersil Corporation

HSP9520 Multilevel Pipeline Registers

NAME VCC GND CLK DIP PIN 24 12 11 I TYPE DESCRIPTION The +5V Power Supply Pin. A 0.1µF capacitor between the VCC and GND pin is recommended. The device ground. Input Clock. Data is latched on the low to high transition of this clock signal. Input setup and hold times with respect to the clock must be met for proper operation. Data Input Port. These inputs a.

Features

• Four 8-Bit Registers
• Hold, Transfer and Load Instructions
• Single 4-Stage or Dual-2 Stage Pipelining
• All Register Contents Available at Output
• Fully TTL Compatible
• Three-State Outputs
• High Speed, Low Power CMOS Applications
• Array Processor
• Digital Signal Processor
• A/D Buffer
• Telecommunication
• Byte Wide Shift Register
• Mainframe Computers Pinout HSP9520, HSP9521 (SOIC, PDIP) TOP VIEW I0 1 I1 2 24 VCC 23 S0 22 S1 21 Y0 20 Y1 19 Y2 18 Y3 17 Y4 16 Y5 15 Y6 14 Y7 13 OE Ordering Information PART NUMBER HSP9520CP HSP9520CS HSP9521CP HSP9521CS TEMP. RANGE (oC) 0 to 70 0 to 7.