HD74HCT138 - Hitachi Semiconductor

HD74HCT138 3-to-8-line Decoder/Demultiplexer

The HD74HCT138 has 3 binary select inputs (A, B, and C). If the device is enabled these inputs determine which one of the eight normally high outputs will go low. Two active low and one active high enables (G1, G2A and G2B) are provided to ease the cascading of decoders. Features • • • • • • LSTTL Output Logic Level Compatibility as well as CMOS Output Comp.

Features

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• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (A, B, C to Y) = 18.5 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HCT138 Function Table Inputs Enable G1 X X L H H H H H H H H G2A X H X L L L L L L L L G2B H X X L L L L L L L L Select C X X X L L L L H H H H B X X X L L H H L L H H A X X X L H L H L H L H Outputs Y0 H H H L H H H H H H H Y1 H H H H L H H H H H H Y2 H H.