EMP19K03HPC - Excelliance MOS

EMP19K03HPC Dual N-Channel Logic Level Enhancement Mode Field Effect Transistor

Q1 Q2 BVDSS 30V 30V RDSON (MAX.)@VGS=10V RDSON (MAX.)@VGS=4.5V 6.6mΩ 2.4mΩ 8.8mΩ 3.4mΩ ID @TC=25℃ 47.0A 93.0A ID @TA=25℃ 16.0A 27.0A Dual N Channel MOSFET UIS, Rg 100% Tested Pb-Free Lead Plating & Halogen Free ▪ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS Q1 Q2 Gate-Source Voltage .

Features

UIS testing in condition of VD=15V, L=0.1mH, VG=10V, IL=21A, Rated VDS=30V N-CH_Q1 ▪100% UIS testing in condition of VD=15V, L=0.1mH, VG=10V, IL=39A, Rated VDS=30V N-CH_Q2 ▪THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM Q1 Q2 Junction-to-Case RθJC Junction-to-Ambient3 t≦10s RθJA Steady-State RθJA 1Pulse width limited by maximum junction temperature. 2Duty cycle < 1％ 365°C / W when mounted on a 1 in2 pad of 2 oz copper. 4Guarantee by Engineering test 5 3.5 40 40 65 65 UNIT V A mJ W W °C UNIT °C/W 2020/8/12 P.1 A.1 EMP19K03HPC ▪Q1_ELECTRICAL C.