EMP18K03HPCS - Excelliance MOS

EMP18K03HPCS Dual N-Channel Logic Level Enhancement Mode Field Effect Transistor

Q1 Q2 BVDSS 30V 30V RDSON (MAX.)@VGS=10V RDSON (MAX.)@VGS=4.5V 5.7mΩ 2.0mΩ 8.8mΩ 2.8mΩ ID @TC=25℃ 52A 88A ID @TA=25℃ 18A 26A Dual N Channel MOSFET UIS, Rg 100% Tested Pb-Free Lead Plating & Halogen Free ▪ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS Q1 Q2 Gate-Source Voltage Cont.

Features

tg -55 to 150 ▪100% UIS testing in condition of VD=15V, L=0.01mH, VG=10V, IL=54A, Rated VDS=30V N-CH_Q1 ▪100% UIS testing in condition of VD=15V, L=0.01mH, VG=10V, IL=70A, Rated VDS=30V N-CH_Q2 ▪THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM Q1 Q2 Junction-to-Case RθJC Junction-to-Top Steady-State RθJT Junction-to-Ambient3 t≦10s RθJA Steady-State RθJA 1Pulse width limited by maximum junction temperature. 2Duty cycle < 1％ 365°C / W when mounted on a 1 in2 pad of 2 oz copper. 4Guarantee by Engineering test 5 3.5 42 30 40 40 65 65 2021/3/31 A.