EM68916CWQA - Etron Technology

EM68916CWQA 8M x 16 bit DDRII Synchronous DRAM

Table 3. Ball Descriptions Symbol CK, CK# Type Input Description EM68916CWQA Differential Clock: CK, CK# are driven by the system clock. All SDRAM input signals are sampled on the crossing of positive edge of CK and negative edge of CK#. Output (Read) data is referenced to the crossings of CK and CK# (both directions of crossing). Clock Enable: CKE activa.

Features

• JEDEC Standard Compliant
• JEDEC Standard 1.8V I/O (SSTL_18-compatible)
• Power supplies: VDD & VDDQ = +1.8V ± 0.1V
• Operating temperatue: 0
  – 85 °C
• Supports JEDEC clock jitter specification
• Fully synchronous operation
• Fast clock rate: 266/333/400MHz
• Differential Clock, CK & CK#
• Bidirectional single/differential data strobe -DQS & DQS# 4
• internal banks for concurrent operation
• 4-bit prefetch architecture
• Internal pipeline architecture
• Precharge & active power down
• Programmable Mode & Extended Mode registers
• Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5
• CAS# Lat.