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Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power (+5V ±10%) Ground Not Connected A0-18 WE# CS# OE# BLOCK DIAGRAM Memory Array Address Buffer Address Decoder I/O Circuits I/O0-7 Microsemi Corporation reserves the right to change products or specifications without notice. May 2014 © 2014 Microsemi Corporation. All rights.
512Kx8 bit CMOS Static
Random Access Memory
• Access Times of 70, 85, 100ns
• Data Retention Function (LP version)
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
32 lead JEDEC Approved Evolutionary Pinout
• Ceramic Sidebrazed 600 mil DIP (Package 9)
• Ceramic SOJ (Package 140)
Single +5V (±10%) Supply Operation
The EDI88512C is a 4 megabit Monolithic CMOS Static RAM. The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. Both the DIP and CSOJ packages are pin for pin upgrades for the single chip enable 128K x 8, the EDI88128C. .
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | EDI88512CA |
ETC |
512Kx8 Monolithic SRAM/ SMD 5962-95600 |
|
| 2 | EDI88512CA |
Microsemi |
512Kx8 Monolithic SRAM |
|
| 3 | EDI88512CA-XMXG |
Microsemi |
512Kx8 Plastic Monolithic SRAM CMOS |
|
| 4 | EDI8808CA35 |
EDI |
High Speed 64K Monolithic SRAM |
|
| 5 | EDI8808CA45 |
EDI |
High Speed 64K Monolithic SRAM |
|
| 6 | EDI8808CA55 |
EDI |
High Speed 64K Monolithic SRAM |
|
| 7 | EDI8808CA70 |
EDI |
High Speed 64K Monolithic SRAM |
|
| 8 | EDI8810H |
EDI |
Low Power 6T CMOS Monolithic SRAM |
|
| 9 | EDI8810L |
EDI |
Low Power 6T CMOS Monolithic SRAM |
|
| 10 | EDI88128C |
ETC |
128K X 8 STATIC RAM CMOS MONOLITHIC |
|
| 11 | EDI88128C |
White Electronic Designs |
128Kx8 MONOLITHIC SRAM |
|
| 12 | EDI88128CS |
White Electronic Designs |
128Kx8 Monolithic SRAM |
|