DS99R103 - National Semiconductor

DS99R103 (DS99R103 / DS99R104) DC-Balanced 24-Bit LVDS Serializer and Deserializer

The DS99R103/104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that i.

Features

pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
■ Internal DC Balancing encode/decode
  – Supports AC
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■ Features www.DataSheet4U.com
■ 3 MHz
  –40 MHz clock embedded and DC-Balancing 24:1 and 1:24 data transmissions
■ Capable to drive shielded twisted-pair cable
■ User selectable clock edge for parallel data on both Transmitter and Receiver coupling interface with no external coding required Individual power-down controls for both Transmitter and Receiver Embed.