DS99R101 - National Semiconductor

DS99R101 (DS99R101 / DS99R102) 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

The DS99R101/DS99R102 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths t.

Features

■ 3 MHz
  –40 MHz clock embedded and DC-Balancing 24:1 and 1:24 data transmissions Transmitter and Receiver
■ User selectable clock edge for parallel data on both coupling interface with no external coding required Individual power-down controls for both Transmitter and Receiver Embedded clock CDR (clock and data recovery) on Receiver and no external source of reference clock needed All codes RDL (random data lock) to support livepluggable applications LOCK output flag to ensure data integrity at Receiver side Balanced TSETUP/THOLD between RCLK and RDATA on Receiver side PTO (progressive turn-o.