CY7C1423KV18 - Cypress Semiconductor

CY7C1423KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture

CY7C1423KV18/CY7C1424KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features ■ 36-Mbit density (2M × 18, 1M × 36) ■ 333 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz ■ Two input clocks .

Features

■ 36-Mbit density (2M × 18, 1M × 36)
■ 333 MHz clock for high bandwidth
■ Two-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed systems
■ Synchronous internally self timed writes
■ DDR II operates with 1.5 cycle read latency when DOFF is asserted HIGH
■ Operates similar to DDR I device w.