The CY7C1418KV18, and CY7C1420KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both.
■ 36-Mbit density (2M × 18, 1M × 36)
■ 333 MHz clock for high bandwidth
■ Two-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Synchronous internally self-timed writes
■ DDR II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to DDR-I device w.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | CY7C1420AV18 |
Cypress Semiconductor |
(CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture | |
2 | CY7C1420BV18 |
Cypress Semiconductor |
(CY7C14xxBV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture | |
3 | CY7C1420JV18 |
Cypress Semiconductor |
(CY7C14xxJV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture | |
4 | CY7C142 |
Cypress Semiconductor |
2K x 8 Dual-Port Static RAM | |
5 | CY7C1421AV18 |
Cypress Semiconductor |
1.8V Synchronous Pipelined SRAM | |
6 | CY7C1422AV18 |
Cypress Semiconductor |
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture | |
7 | CY7C1422BV18 |
Cypress Semiconductor |
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture | |
8 | CY7C1422JV18 |
Cypress Semiconductor |
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture | |
9 | CY7C1423AV18 |
Cypress Semiconductor |
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture | |
10 | CY7C1423BV18 |
Cypress Semiconductor |
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture | |
11 | CY7C1423JV18 |
Cypress Semiconductor |
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture | |
12 | CY7C1423KV18 |
Cypress Semiconductor |
36-Mbit DDR II SIO SRAM Two-Word Burst Architecture |