The CDCLVD2106 clock buffer distributes two clock inputs (IN0, IN1) to a total of 12 pairs of differential LVDS clock outputs (OUT0, OUT11). Each buffer block consists of one input and 6 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS. The CDCLVD2106 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs i.
1
• Dual 1:6 Differential Buffer
• Low Additive Jitter: <300 fs rms
in 10 kHz
– 20 MHz
• Low Within Bank Output Skew of 45 ps (Max)
• Universal Inputs Accept LVDS, LVPECL,
LVCMOS
• One Input Dedicated for Six Outputs
• Total of 12 LVDS Outputs, ANSI EIA/TIA-644A
Standard Compatible
• Clock Frequency up to 800 MHz
• 2.375
–2.625 V Device Power Supply
• LVDS Reference Voltage, VAC_REF, Available for
Capacitive Coupled Inputs
• Industrial Temperature Range
–40°C to 85°C
• Packaged in 6 mm x 6 mm 40-pin QFN (RHA)
• ESD Protection Exceeds 3-kV HBM, 1-kV CDM
APPLICATIONS
• Telecommunications/Networki.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | CDCLVD2102 |
Texas Instruments |
Dual 1:2 Low Additive Jitter LVDS Buffer | |
2 | CDCLVD2104 |
Texas Instruments |
Dual 1:4 Low Additive Jitter LVDS Buffer | |
3 | CDCLVD2108 |
Texas Instruments |
Dual 1:8 Low Additive Jitter LVDS Buffer | |
4 | CDCLVD110 |
Texas Instruments |
PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER | |
5 | CDCLVD110A |
Texas Instruments |
PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER | |
6 | CDCLVD1204 |
Texas Instruments |
2:4 Low Additive Jitter LVDS Buffer | |
7 | CDCLVD1208 |
Texas Instruments |
2:8 Low Additive Jitter LVDS Buffer | |
8 | CDCLVD1212 |
Texas Instruments |
2:12 Low Additive Jitter LVDS Buffer | |
9 | CDCLVD1213 |
Texas Instruments |
1:4 Low Additive Jitter LVDS Buffer | |
10 | CDCLVD1216 |
Texas Instruments |
2:16 Low Additive Jitter LVDS Buffer | |
11 | CDCLVC1102 |
Texas Instruments |
3.3-V and 2.5-V LVCMOS High-Performance Clock Buffer | |
12 | CDCLVC1103 |
Texas Instruments |
3.3-V and 2.5-V LVCMOS High-Performance Clock Buffer |