The CDCLVD110 clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVD110 is specifically designed for driving 50-Ω transmission lines. When the control enable is high (EN = 1), the 10 differential outputs are programmable .
1
• Low-Output Skew <30 ps (Typical) for Clock-Distribution Applications
• Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs
• VCC range 2.5 V ±5%
• Typical Signaling Rate Capability of Up to
1.1 GHz
• Configurable Register (SI/CK) Individually Enables Disables Outputs, Selectable CLK0, CLK0 or CLK1, CLK1 Inputs
• Full Rail-to-Rail Common-Mode Input Range
• Receiver Input Threshold ±100 mV
• Available in 32-Pin LQFP Package
• Fail-Safe I/O-Pins for VDD = 0 V (Power Down)
LQFP PACKAGE
DESCRIPTION
The CDCLVD110 clock driver distributes one pair of differential LVDS.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | CDCLVD110A |
Texas Instruments |
PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER | |
2 | CDCLVD1204 |
Texas Instruments |
2:4 Low Additive Jitter LVDS Buffer | |
3 | CDCLVD1208 |
Texas Instruments |
2:8 Low Additive Jitter LVDS Buffer | |
4 | CDCLVD1212 |
Texas Instruments |
2:12 Low Additive Jitter LVDS Buffer | |
5 | CDCLVD1213 |
Texas Instruments |
1:4 Low Additive Jitter LVDS Buffer | |
6 | CDCLVD1216 |
Texas Instruments |
2:16 Low Additive Jitter LVDS Buffer | |
7 | CDCLVD2102 |
Texas Instruments |
Dual 1:2 Low Additive Jitter LVDS Buffer | |
8 | CDCLVD2104 |
Texas Instruments |
Dual 1:4 Low Additive Jitter LVDS Buffer | |
9 | CDCLVD2106 |
Texas Instruments |
Dual 1:6 Low Additive Jitter LVDS Buffer | |
10 | CDCLVD2108 |
Texas Instruments |
Dual 1:8 Low Additive Jitter LVDS Buffer | |
11 | CDCLVC1102 |
Texas Instruments |
3.3-V and 2.5-V LVCMOS High-Performance Clock Buffer | |
12 | CDCLVC1103 |
Texas Instruments |
3.3-V and 2.5-V LVCMOS High-Performance Clock Buffer |