CD54HC195 - Texas Instruments

CD54HC195 4-Bit Parallel Access Register

• Asynchronous Master Reset • J, K, (D) Inputs to First Stage • Fully Synchronous Serial or Parallel Data Transfer • Shift Right and Parallel Load Capability • Complementary Output From Last Stage • Buffered Inputs • CTyLp=ic1a5l pfMF,ATXA==5205MoHCz at VCC = 5V, • Fanout (Over Temperature Range) - Standard Outputs . . . . . . 10 LSTTL Loa.

Features

Description
• Asynchronous Master Reset
• J, K, (D) Inputs to First Stage
• Fully Synchronous Serial or Parallel Data Transfer
• Shift Right and Parallel Load Capability
• Complementary Output From Last Stage
• Buffered Inputs
• CTyLp=ic1a5l pfMF,ATXA==5205MoHCz at VCC = 5V,
• Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs.