This device contains three independent 3-input AND gates. Each gate performs the Boolean function Y = A ● B ● C in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HC11M SOIC (14) 8.70 mm × 3.90 mm CD74HC11E PDIP (14) 19.30 mm × 6.40 mm CD54HC11F CDIP (14) 21.30 mm × 7.60 mm (1) For all available packages, see the .
• Buffered inputs
• Wide operating voltage range: 2 V to 6 V
• Wide operating temperature range:
–55°C to +125°C
• Supports fanout up to 10 LSTTL loads
• Significant power reduction compared to LSTTL
logic ICs
2 Applications
• Combining power good signals
• Enable digital signals
1A
1
1B
2
2A
3
2B
4
5 2C
2Y
6
GND
7
3 Description
This device contains three independent 3-input AND gates. Each gate performs the Boolean function Y = A
● B
● C in positive logic.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CD74HC11M
SOIC (14)
8.70 mm × 3.90 mm
CD74HC11E
PDIP (14.
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